Previous logic systems, such as boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. Typically, a logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the circuit, the circuit output is unreliable for a period of time corresponding to worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is set according to an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
Asynchronous circuits have been proposed that are intended to operate without an independent clock. One asynchronous logic paradigm is disclosed in U.S. Pat. No. 5,305,463 ("NULL Convention Logic"), which is incorporated herein by reference in its entirety. This paradigm uses logic gates referred to as threshold gates. Within this class, circuits are made with gates having varying numbers of inputs, and varying threshold values.
It is desirable to have a complete family of gates available for rapid prototyping and testing of multi-gate asynchronous circuits. Fabrication of custom integrated circuits is a method for producing a complete family of gates, however, custom fabrication involves turn-around time and cost. A faster and less costly approach to implementing a wide variety of threshold gates is desirable.